1. Field of the Invention
The present invention relates to a substrate for a semiconductor device and a method of fabricating a semiconductor device comprising the substrate and a semiconductor element or an integrated circuit (IC) chip mounted thereon. More particularly, the invention relates to a substrate comprising a dielectric base material (or, a dielectric core), inner terminals for electrical connection to the semiconductor element or chip, an inner circuit electrically connected to the inner terminals, and external terminals electrically connected to the inner circuit for electrical connection to an external circuit provided outside the substrate, and a method of fabricating a semiconductor device using the substrate.
2. Description of the Related Art
In recent years, there has been the increasing need to mount a semiconductor element or IC chip and its relating electronic components on a substrate at higher density. To meet this need, the Ball Grid Array (BGA) package and the Land Grid Array (LGA) package have been developed and used practically, thereby reducing the mounting area of the packaged semiconductor device including the element or chip.
The BGA package is a type of the surface-mounting packages of the semiconductor device, in which a semiconductor element or elements is/are mounted on a substrate and electrically connected to the inner circuit of the substrate. The element or elements and the substrate are encapsulated with a resin material in such a way that the bottom of the substrate is exposed from the encapsulation material, forming a surface-mounting package. Electrodes, which are electrically connected to the element or elements, are formed on the flat bottom of the package (i.e., the substrate) in the form of grid array. Metal or conductive balls (e.g., solder bumps) are attached to the respective electrodes as external terminals for electrical connection to an external circuit provided outside the package.
The LGA package is another type of the surface-mounting packages of the semiconductor device, in which a semiconductor element or elements is/are mounted on a substrate and electrically connected to the inner circuit of the substrate. The element or elements and the substrate are encapsulated with a resin material in such a way that the bottom of the substrate is exposed from the encapsulating material, forming a surface-mounting package. This configuration is the same as the BGA package. Unlike this, Electrode pads (i.e., lands), which are electrically connected to the element or elements, are formed on the flat bottom of the package (i.e., the substrate) in the form of grid array. The pads or lands serve as the external terminals and thus, no metal balls (i.e., bumps) are attached thereto.
FIGS. 1 and 2 show an example of the conventional substrate used for the semiconductor device with the surface-mounting packages of this type. FIG. 1 shows the top view of a part of the substrate while FIG. 2 shows the bottom view thereof.
The conventional substrate 110 shown in FIGS. 1 and 2 comprises a rectangular plate-shaped, rigid, dielectric core 111 having an upper surface and a lower surface. The core 111 has a mounting area 111a on its upper surface and a land area 111b on its lower surface. A semiconductor element or IC chip (not shown) is mounted in the mounting area 111a in a later process. Lands 120 as external terminals are arranged in the form of array in the land area 111b, as shown in FIG. 2. The core 111 is typically made of dielectric material, such as woven glass cloth impregnated with epoxy resin.
A patterned, conductive layer is formed on the upper surface of the core 111, forming inner wiring lines 113 and inner terminals 114. The conductive layer is typically made of a copper foil that has been etched to have a desired pattern. The wiring lines 113 extend approximately radially from the neighborhood of the periphery of the area 111a toward the outside. The terminals 114, which are located in the mounting area 111a, are connected to the inner ends of the respective wiring lines 113. The terminals 114 are used for electrically connection to a semiconductor element or an IC chip (nor shown) to be mounted on the substrate 110 by way of thin metal wires.
A conductive runner 117 is formed on the upper surface of the core 111. The runner 117 is located near one of the edges of the core 111 and electrically connected to part of the inner wiring lines 113. The runner 117 is used for facilitating the separation of the substrate 110 in a molding process of a semiconductor element or an IC chip mounted on the core 111.
Another patterned, conductive layer is formed on the lower surface of the core 111, forming inner wiring lines 119 and external terminals or lands 120. The conductive layer is typically made of a copper foil that has been etched to have a desired pattern. The wiring lines 119 extend approximately radially from the inside of the land area 111b toward the outside. The terminals or lands 120 are connected to the inner ends of the respective wiring lines 119 and located in the area 111b. The lands 120 are used for electrically connection to an external circuit provided outside the substrate 110.
Through holes 115 are formed to vertically penetrate the core 111 to interconnect the upper and lower surfaces of the core 111 with each other. The upper openings of the holes 115 are overlapped with the respective wiring lines 113 outside the mounting area 111a while the lower openings of the holes 115 are overlapped with the respective wiring lines 119. Although not shown, the inner surfaces of the respective holes 115 are covered with a conductive layer such as a plated solder layer, in other words, the holes 115 are so-called xe2x80x9cplated through holesxe2x80x9d. Therefore, the wiring lines 113 on the upper surface of the core 111 are electrically connected to the respective wiring lines 119 on the lower surface thereof.
In the configuration shown FIGS. 1 and 2, the core 111 has a simple dielectric layer including no wiring layers therein. However, if the core 111 has a multilayer wiring structure including inner wiring layers and inner dielectric layers laminated together, the through holes 115 are used to electrically connect the specific wiring lines 113 and 119 to the inner wiring lines as well.
The upper surface of the core 111 is entirely covered with a dielectric, solder resist layer 118 except for the region 118a exposing the mounting area 111a and the region 118b exposing the runner 117. The lower surface of the core 111 is entirely covered with a dielectric, solder resist layer 122 except for the region exposing the lands 120. Therefore, the wiring lines 113 and 119 and the top and bottom openings of the through holes 115 are actually invisible from the outside. However, to clarify the configuration of the substrate 110, they are illustrated to be visible in FIGS. 1 and 2.
Additionally, the core 111 is typically formed to be a strip, including a plurality of the structure shown in FIGS. 1 and 2. In this case, the structure of FIGS. 1 and 2 are usually aligned at equal intervals in a single direction on the core 111.
When a semiconductor device is fabricated using the substrate 110, a specific semiconductor element or IC chip (not shown) is mounted on the upper surface of the substrate 110 (i.e., the core 111) in the mounting area 111a. Next, the electrodes or bonding pads of the element or chip and the inner terminals 114 are mechanically and electrically connected to each other with thin metal wires (not shown). Thereafter, the element or chip, the metal wires, and the terminals 114 are encapsulated with a sealing or encapsulating resin material (not shown) on the upper surface of the substrate 110. If the core 111 includes a plurality of the structure shown in FIGS. 1 and 2, these process steps are conducted for each of the mounting areas 111a on the substrate 110. Finally, the substrate 110 with the elements or chips is divided into pieces, thereby forming the semiconductor devices as desired.
With the above-described conventional substrate 110 shown in FIGS. 1 and 2, the formation of the individual inner wiring lines 113 and 119, the inner terminals 114, and the external terminals or lands 120 formed on the core 111 has been completed. In other words, unlike the packaged semiconductor devices using leadframes where the lead fingers are kept electrically short-circuited until the fabrication process sequence is finalized, the lines 113 and 119, the terminals 114, and the lands 120 are kept in an electrically floating state during the fabrication process sequence. For this reason, if the substrate 110 undergoes electrical energy from the outside due to plasma processing or the like, or the substrate 110 itself is slid across or contacted with an adjoining part or member of the fabrication system during the transportation process or any subsequent process, the lines 113 and 119, the terminals 114, and the lands 120 are likely to be electrified. If so, when the electric charge on the substrate 110 is discharged instantaneously, the charge will pass through the semiconductor element or IC chip mounted on the substrate 110, resulting in the danger that the element or chip is broken electrostatically.
To solve the problem of the danger that the element or chip is broken electrostatically, various techniques have been developed. An example of the improved techniques was disclosed in the Japanese Non-Examined patent Publication No 11-340592 published in December 1999.
In the improved technique disclosed in the Publication No. 11-340592, a short-circuiting line or pattern is formed in the periphery of a printed wiring board on which a semiconductor element (i.e., an IC chip) is mounted. The short-circuiting line or pattern causes electrical short-circuit among the terminals formed on the board, thereby keeping the terminals in the same electric potential. Thus, even if the board is electrified electrostatically due to the same cause as above during the fabrication process sequence, the semiconductor element or IC chip mounted on the board is prevented from being broken electrostatically.
The short-circuiting line or pattern is cut or removed to eliminate the electrically short-circuited state among the terminals in a later step of the fabrication process sequence.
With the improved technique disclosed in the Publication No. 11-340592, however, there are the following problems.
First, with the improved technique, there is the need to form the short-circuiting line or pattern in such a way that part of the terminals are selectively short-circuited according to necessity. Therefore, when the improved technique is applied to the substrates of the type designed for semiconductor devices with the BGA or LGA package, it is often difficult to provide a space or room for the short-circuiting line or pattern on the substrate. This is because the wiring lines are arranged on the substrate at a considerably high density. As a results it is seen that the improved technique is difficult to be applied to the substrates for the BGA- or LGA-packaged semiconductor devices.
Second, since the terminals on the printed wiring board are short-circuited with the short-circuiting line or pattern, desired electrical tests for inspection are unable to be carried out just after a semiconductor element or IC chip is mounted.
Third, even if the terminals on the board are short-circuited with the short-circuiting line or pattern, the board itself is kept in an electrically floating state. Thus, it is difficult to release the electric charge from the terminals. This means that it is difficult or unable to surely prevent the semiconductor element or IC chip from being broken or damaged electrostatically.
Fourth, the improved technique necessitates a dedicated process of eliminating the short-circuiting line or pattern. Thus, the total step number of the fabrication process sequence increases.
Accordingly, an object of the present invention is to provide a substrate for a semiconductor device that prevents a semiconductor element or IC chip mounted thereon from being broken or damaged electrostatically in a fabrication process sequence of the semiconductor device, and a method of fabricating a semiconductor device using the substrate.
Another object of the present invention is to provide a substrate for a semiconductor device that eliminates easily the electrified state of the substrate in the fabrication process sequence of the semiconductor device, and a method of fabricating a semiconductor device using the substrate.
Still another object of the present invention is to provide a substrate for a semiconductor device that is applicable to a semiconductor device with high-density wiring lines, and a method of fabricating a semiconductor device using the substrate.
A further object of the present intention is to provide a substrate for a semiconductor device that makes it possible to conduct desired electric tests of a semiconductor device in its fabrication process sequence, and a method of fabricating a semiconductor device using the substrate.
A still further object of the present invention is to provide a substrate for a semiconductor device that requires no additional process in the fabrication process sequence of a semiconductor device, and a method of fabricating a semiconductor device using the substrate.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
According to a first aspect or the present invention, a substrate for a semiconductor device is provided. This substrate comprises:
(a) a dielectric core material with a first surface and a second surface;
the core material having a mounting area on the first surface;
the mounting area being used for mounting a semiconductor element on the first surface;
the core material having a contact area;
(b) inner terminals formed on the first surface of the core material;
the inner terminals used for electrical connection to a semiconductor element if mounted on the mounting area of the core material;
(c) external terminals formed on the second surface of the core material;
the external terminals being used for electrical connection to an external circuit provided outside the substrate; and
(d) inner wiring lines formed on the core material;
the inner wiring lines connecting electrically the inner terminals to the respective external terminals;
at least one of the Inner wiring lines extending to the contact area of the core material in such a way as to be able to contact an external conductor provided outside the substrate.
With the substrate according to the first aspect of the invention, the dielectric core material has the contact area along with the mounting area. The at least one of the inner wiring lines extends to the contact area in such a way as to be able to contact an external conductor provided outside the substrate.
Therefore, even if the substrate undergoes electrification due to some cause in a fabrication process sequence of the device and it holds electric charge, the electric charge held on the substrate will be discharged by simply contacting the at least one of the inner wiring lines located in the contact area with an external conductor provided outside the substrate (e.g., a transporting rail of a fabrication system). As a result, the electrified state of the substrata is easily eliminated in the fabrication process sequence of the semiconductor device. This means that the semiconductor element mounted on the core in its mounting area is prevented from being broken or damaged electrostatically in a fabrication process sequence of a semiconductor device.
Moreover, since the short-circuiting line or pattern disclosed in the Publication No. 11-340592 referred previously is unnecessary, the substrate according to the first aspect is applicable to a semiconductor device with high-density wiring lines. Also, due to the same reason, desired electric tests of a semiconductor device can be conducted in its fabrication process sequence.
Furthermore, the contact area of the core material can be selectively removed from the same in the process of removing the extra part of the core material and therefore, no additional process is required.
In a preferred embodiment of the substrate according to the first aspect, a first dielectric layer and a second dielectric layer are additionally provided. The first dielectric layer is formed to cover the first surface of the core material except for the mounting area, the contact area, and the inner terminals. The second dielectric layer is formed to cover the second surface of the core material except for the external terminals.
In this embodiment, preferably, each of the first and second dielectric layers is a solder resist layer.
In another preferred embodiment of the substrate according to the first aspect, the inner wiring lines located in the contact area are not electrically short-circuited with each other.
In still another preferred embodiment of the substrate according to the first aspect, the contact area is located on at least one of the first surface of the core material and the second surface thereof.
In this embodiment, the contact area is located near an edge of the core material.
In a further preferred embodiment of the substrate according to the first aspect, the contact area is located on a side of the core material that interconnects the first and second surfaces of the core material.
In this embodiment, it is preferred that through holes are additionally formed to interconnect the first and second surfaces of the core material. Inner surfaces of the holes are covered with conductive layers. The conductive layers are electrically connected to the respective inner wiring lines.
In a still further preferred embodiment of the substrate according to the first aspect, combination of the mounting area of the core material, the inner terminals, the external terminals, and the inner wiring lines constitute a device formation assembly. An additional device formation assembly having the same configuration as the device formation assembly is provided on the core material at a specific interval.
According to a second aspect of the present invention, another substrate for a semiconductor device is provided. This substrate comprises:
(a) a dielectric core material with a first surface and a second surface;
the core material having mounting areas on the first surface;
each of the mounting areas being used for mounting a semiconductor element on the first surface;
the core material having a contact area;
(b) sets of inner terminals formed on the first surface of the core material for the respective mounting areas;
each of the sets of inner terminals being used for electrical connection to a semiconductor element if mounted on one of the mounting areas of the core material;
(c) sets of external terminals formed on the second surface of the core material;
each of the sets of external terminals being used for electrical connection to an external circuit provided outside the substrate; and
(d) sets of inner wiring lines formed on the core material;
each of the sets of inner wiring lines connecting electrically one of the sets of inner terminals with a corresponding one of the sets of external terminals;
at least one of each of the sets of inner wiring lines extending to the contact area of the core material in such a way as to be able to contact an external conductor provided outside the substrate;
wherein each of the mounting areas of the core material, a corresponding one of the sets of inner terminals, a corresponding one of the sets of external terminals, and a corresponding one of the sets of inner wiring lines constitute a device formation assembly.
With the substrate according to the second aspect of the invention, the mounting areas, the sets of inner terminals, the sets of external terminals, and the sets of inner wiring lines are formed on the core material. Each of the mounting areas, a corresponding one of the sets of inner terminals, a corresponding one of the sets of external terminals, and a corresponding one of the sets of inner wiring lines constitute the device formation assembly. The combination of the core material and each of the device formation assemblies corresponds approximately to the substrate of the first aspect.
Thus, it is said that the combination of the core material and each of the device formation assemblies in the substrate of the second aspect has substantially the same configuration as that of the substrate of the first aspect. As a result, the substrate of the second aspect has the same advantages as those of the substrate according to the first aspect.
In a preferred embodiment of the substrate according to the second aspect, a first dielectric layer and a second dielectric layer are additionally provided. The first dielectric layer is formed to cover the first surface of the core material except for the mounting areas, the sets of contact areas, and the sets of inner terminals. The second dielectric layer is formed to cover the second surface of the core material except for the sets of external terminals.
In this embodiment, preferably, each of the first and second dielectric layers is a solder resist layer.
In another preferred embodiment of the substrate according to the second aspect, the sets of inner wiring lines located in the contact area are not electrically short-circuited with each other.
In still another preferred embodiment of the substrate according to the second aspect, the contact area is located on at least one of the first surface of the core material and the second surface thereof.
In this embodiment, the contact area is located near an edge of the core material.
In a further preferred embodiment of the substrate according to the second aspect, the contact area is located on a side of the core material that interconnects the first and second surfaces of the core material.
In this embodiment, it is preferred that through holes are additionally formed to interconnect the first and second surfaces of the core material. Inner surfaces of the holes are covered with conductive layers. The conductive layers are electrically connected to the respective sets of inner wiring lines.
In a still further preferred embodiment of the substrate according to the second aspect, the device formation assemblies are arranged at regular intervals along an axis of the core material. The contact area is commonly used for all the device formation assemblies.
According to a third aspect of the present invention, a method of fabricating a semiconductor device using the substrate according to the second aspect is provided. This method comprises the steps of:
(a) providing a substrate according to the second aspect of the invention;
(b) mounting a semiconductor element on each of the mounting areas of the substrate;
(c) making electrical interconnection between the semiconductor element mounted in each of the mounting areas and a corresponding one of the sets of inner terminals; and
(d) cutting the substrate to separate the device formation assemblies including the respective semiconductor elements from each other, thereby forming semiconductor devices;
the contact area of the substrate being separated from all the semiconductor devices in the process of cutting the substrate.
With the method of fabricating a semiconductor device according to the third aspect of the invention, after the substrate according to the second aspect is provided, the semiconductor element is mounted on each of the counting areas of the substrate, electrical interconnection is made between the semiconductor element mounted in each of the mounting areas and a corresponding one of the sets of inner terminals, and substrate is cut to separate the device formation assemblies including the respective semiconductor elements from each other, thereby forming semiconductor devices.
Therefore, the electrified state of the substrate is easily eliminated in the fabrication process sequence of the semiconductor device. This means that the semiconductor elements mounted on the substrate are prevented from being broken or damaged electrostatically in the fabrication process sequence.
Also, since the substrate according to the second aspect is used, the semiconductor device with high-density wiring lines can be fabricated and at the same time, desired electric tests of the semiconductor device can be conducted in its fabrication process sequence.
Additionally, the contact area of the substrate is separated from all the semiconductor devices in the step (d) of cutting the substrate and therefore, no additional process is required in the fabrication process sequence of the device. In other words, the total number of the necessary fabrication process steps does not increase.
In a preferred embodiment of the method according to the third aspect, the substrate is cut in the step (d) in such a way that cutting action progresses along a cutting line that surrounds each of the device formation assemblies. The contact area of the core material is excluded from all the cutting lines.